About
# About the Role Intel Corporation, a global leader in semiconductor manufacturing and computing innovation, has a strong presence in India with multiple R&D centers, design studios, and manufacturing collaborations. Our Bangalore campus focuses on cutting-edge chip design, advanced process development, and next-generation architecture that powers everything from data centers to consumer devices. Intel’s Indian engineering teams work closely with global product groups, offering fresh graduates exposure to world-class technology, cross-functional collaboration, and a culture that encourages continuous learning. As a Physical Design Layout Engineer, you will be an integral part of Intel’s semiconductor engineering business. You will join a team that translates logical netlists into physical silicon layouts, ensuring that the design meets performance, power, and reliability targets. You will receive mentorship from senior layout engineers and gain hands-on experience with industry-leading EDA tools, design rule checks, and verification flows. This position is hybrid, allowing you to work from the Bangalore office while also leveraging remote resources for focused design tasks. ## Key Responsibilities - Develop semi-custom cell and block level layouts using ICC2 and related tools. - Perform floor-planning at the functional unit block (FUB) level and generate abstract views for higher-level integration. - Execute schematic-to-layout verification (DRC, LVS) to ensure design integrity. - Conduct parasitic extraction and analyze its impact on timing and power. - Create and edit custom polygons, and fine-tune routing using auto-place & route algorithms. - Collaborate with circuit designers, verification engineers, and process engineers to resolve layout-related issues. - Contribute to the development and improvement of physical design methodologies and verification flows. - Participate in full-chip assembly activities, including placement, routing, and sign-off. - Write and maintain TCL scripts to automate repetitive tasks and improve productivity. - Document design decisions, maintain layout libraries, and ensure compliance with Intel’s design standards. ## Requirements - Proficiency in Physical Design, IC Layout, Layout Verification, Floor Planning, Schematic-to-Layout Verification, Parasitic Extraction, Auto Place & Route, and TCL scripting. - Familiarity with tools such as Synopsys ICC2, Cadence Virtuoso, and Mentor Graphics Calibre for DRC/LVS. - A genuine interest in semiconductor design and a commitment to continuous learning. ## Benefits - A clear growth path starting as a Junior Layout Engineer, progressing to Senior Layout Engineer, then Physical Design Lead or Architecture Specialist. - Opportunities to move into cross-functional system design or project management roles. - A vibrant ecosystem of learning with internal training modules and mentorship programs that accelerate your technical depth. - A commitment to diversity, work-life balance, and employee well-being. - The chance to work on real silicon projects with a tangible impact on products that shape the future of computing.
MATCH FREE