Intel is hiring a Physical Design Layout Engineer to help translate logical netlists into physical silicon layouts for semiconductor products. The role sits within Intel’s Bangalore engineering teams and offers exposure to chip design, verification flows, and collaboration with global product groups on real silicon work.

• Develop semi-custom cell and block level layouts using ICC2 and related tools
• Perform floor-planning at the functional unit block (FUB) level and generate abstract views for higher-level integration
• Execute schematic-to-layout verification (DRC, LVS) to ensure design integrity
• Conduct parasitic extraction and analyze its impact on timing and power
• Collaborate with circuit designers, verification engineers, and process engineers to resolve layout-related issues
• Write and maintain TCL scripts to automate repetitive tasks and improve productivity

• Proficiency in Physical Design, IC Layout, Layout Verification, Floor Planning, Schematic-to-Layout Verification, Parasitic Extraction, Auto Place & Route, and TCL scripting
• Familiarity with Synopsys ICC2, Cadence Virtuoso, and Mentor Graphics Calibre for DRC/LVS
• A genuine interest in semiconductor design
• Commitment to continuous learning

• Hybrid work model from the Bangalore office with remote resources for focused design tasks
• Mentorship from senior layout engineers
• Hands-on experience with industry-leading EDA tools and verification flows
• Clear growth path from Junior Layout Engineer to Senior Layout Engineer, then Physical Design Lead or Architecture Specialist
• Opportunities to move into cross-functional system design or project management roles
• Internal training modules and mentorship programs
• Commitment to diversity, work-life balance, and employee well-being
• Chance to work on real silicon projects with tangible product impact